The present invention relates to a semiconductor integrated circuit of the type having a nonvolatile memory. More particularly, it relates to a technique which leads to an improvement in the enhancement of the speed and a reduction of the power consumption of a nonvolatile memory of the type that is effectively applied to a microcomputer, a system LSI, and the like.
Japanese Unexamined Patent Publication No. Hei 1(1989)-100797, Japanese Unexamined Patent Publication No. Hei 2(1990)-14495, and Japanese Unexamined Patent Publication No. Hei 10(1998)-320993 disclose ROMs (Read Only Memories). These ROMs are so constituted that memory cells having a two-transistor configuration are provided between bit lines, and a complementary output is “read out” to complementary bit lines.
Japanese Unexamined Patent Publication No. Hei 10(1998)-64292 discloses a ROM wherein, in the initial state (standby state), bit line pairs are brought to the level of the ground voltage of the circuit. Japanese Unexamined Patent Publication No. Hei 11(1999)-16384 discloses a masked ROM wherein the source electrode of memory cell transistors is connected to the ground voltage of the circuit, and pulldown circuits are provided for the bit lines of the memory cell transistors.
Japanese Unexamined Patent Publication No. Hei 7(1995)-78489 discloses a masked ROM wherein contacts (ROM's eyes) with memory cell transistors are formed between them and a source line.
Japanese Unexamined Patent Publication No. 2000-012707 discloses a ROM wherein the density of storage cells is enhanced. This enhancement is implemented by forming the ROM of MOS semiconductor devices, which receive the source potential of storage cells (the ground voltage of the circuit) in the (field oxide film) regions between the drains of the storage cells to isolate data between the storage cells.
The present inventors have considered the performance of semiconductor integrated circuits, such as a microcomputer or a system LSI, provided with a ROM and a logic circuit, such as a CPU, and the like, which utilize information stored in the ROM. As a result, the present inventors have found that the following is useful in enhancing the operating performance of the semiconductor integrated circuits: an access rate suitable for the operating speed of a CPU is attained in a ROM, and the power consumption of the ROM is reduced so that the major part of power available to the entire semiconductor integrated circuit can be allocated to the logic circuit. With the enhancement of the speed and packing density of logic circuits, the operating voltage tends to be lowered. In conjunction with this, on-chip ROMs are required to operate on as low a voltage as the logic circuit from the viewpoint of cost and the like. With a lowered operating power supply, an increase in useless power consumption due to a subthreshold leakage current becomes an issue. In addition, it can be difficult to discriminate between a subthreshold leakage current which passes through a lot of unselected memory cells and a current which passes through memory cells selected during memory access. As a result, the reliability of a memory operation and, further, that of a data processing operation utilizing it, will be lost.
An object of the present invention is to provide a semiconductor integrated circuit wherein, even if the voltage of the operating power supply to an on-chip nonvolatile memory is lowered, a stabilization, acceleration, and a power consumption reduction can be accomplished with respect to a read operation on the nonvolatile memory.
Another object of the present invention is to provide a semiconductor integrated circuit wherein, even if the voltage of the operating power supply to an on-chip nonvolatile memory, as well as an on-chip logic circuit, is lowered, an access rate suitable for the operating speed of the logic circuit can be attained in a ROM, and wherein the power consumption of the ROM can be reduced so that the major part of power available to the entire semiconductor integrated circuit can be allocated to the logic circuit.
These and other objects and novel features of the present invention will be apparent from the following description and the accompanying drawings.